Design for Test Engineers

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Company Overview Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide end-to-end solutions in VLSI Design, Test & Product Engineering, and Embedded Systems. We work with leading semiconductor companies worldwide, enabling innovation through deep domain knowledge and engineering excellence. Summary of the Role We are looking for skilled and motivated Design for Test (DFT) Engineers with 4–10 years of experience in developing and implementing advanced DFT methodologies for complex SoCs and ASICs. Key Responsibilities Develop and implement DFT architectures for SoC/ASIC designs. Utilize expertise in Scan Insertion, ATPG, MBIST, LBIST, JTAG, and Boundary Scan. Work on tool flows for Synopsys/Mentor/Cadence DFT tools. Collaborate with RTL, physical design, verification, and test teams to integrate and validate DFT features. Debug and resolve issues during synthesis, simulation, and silicon bring-up. Deliver high-quality test coverage while optimizing for area, power, and performance impact. Support ATE patterns generation and silicon validation. Required Qualifications Must-Have: Strong knowledge of DFT methodologies (Scan, ATPG, BIST, Boundary Scan, JTAG, compression techniques). Hands-on experience with industry-standard DFT EDA tools (Synopsys DFTMAX/TetraMAX, Cadence Modus, Mentor Tessent). Good understanding of RTL design, logic synthesis, timing, and verification. Solid debugging and problem-solving skills across pre-sil

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